Tackling Design for Yield Questions at DAC

Process variations are unavoidable, but how can chip designers plan for them in their designs to obtain optimal yield and device performance? That’s one of the focal points of a pavilion panel at the upcoming Design Automation Conference (DAC), to be held June 2-6 in Austin, TX. Titled "Learn the Secrets of Design for Yield," it will be moderated by yours truly with panelists: Shaofeng Yu of Semiconductor Manufacturing International (SMIC); Dr. Min-Chie Jeng from Taiwan Semiconductor Manufacturing Co. (TSMC); and Dr. Luigi Capodieci from GLOBALFOUNDRIES.

Time and place: Wednesday, June 5^th, from 1:30 to 2:15 pm, Booth #509 on the DAC exhibit floor.

Foundries supply process information to chip designers, but according to Dr. Zhihong Liu, CEO of ProPlus Design Solutions (one of the organizers of the session), this process information is sometimes either too conservative or too optimistic, and the foundry models may be used inappropriately or incorrectly on an application-specific basis. Compounding the problem are selective corner models (i.e., process, voltage and temperature or “PVT” corners) and Monte Carlo analysis approaches often employed by circuit designers may give limited information, giving them low confidence on the yield prediction and design optimization.

The panel will look at advanced process node challenges that highlight increased random process variations and layout-dependent effects designers must address in SoC design. The panel of foundry experts will share techniques to manage these sub-nanometer effects to improve manufacturability and yield.

Liu said Monte Carlo analysis works well, but can be costly because it takes so long to run. In the past, designers have used Monte Carlo analysis for some key components, but now it will be required more often for “all kinds of circuits and components,” Liu said. He added that there are some tricks you can use to ease the pain of Monte Carlo simulation, such as parallelization and advanced algorithms. “People generally use so-called advanced sampling technology. That is a sort of statistical algorithm, trying to not reduce the accuracy of the simulation in terms of statistics, yet still significantly reduce the sampling size so that you don’t need to simulate a thousand or million of times, Liu said.

Design for Yield (DFY) has quite a different meaning to the chip design industry than Design for Manufacturing (DFM). DFM was a common buzzword in the 2004-2005 timeframe, although everyone seemed to define it a bit differently. EDA suppliers eventually came up with a commercial DFM solution, after which the term DFM fell out of favor. DFY today refers to the gap between what the designers think they need to guarantee a reliable design and what the manufacturer or foundry think they need from the designers to be able to manufacture the product in a reliable fashion.

SoCs are clearly getting bigger and more complex. At the Advanced Semiconductor Manufacturing Conference in May, Subi Kengeri, vp of advanced technology architecture at GLOBALFOUNDRIES, said 47% of SoC designs now use more than 5M gates. There are also a larger number of clock domains, which means managing multiple macros operating at different frequencies. There are also more voltage domains across the chip, with five now being the average.

Among the question the DFY DAC panel will address: How do foundries handle variability analysis? What are the conditions for tapeout? Can designers trust the foundry models? Do they need to run Monte Carlo analysis (and if so, how can they speed it up?). How many PVT corners do they need to verify?

Liu says that designers need to have support from CAD vendors, and also they need to have the model variation information from foundries. “If those are well integrated with a reasonable efficiency, the design job will be more suitable for higher yield or a better tradeoff between yield and performance,” he said. If that doesn’t exist (and it often doesn’t) bad things can happen. “Sometimes, if you do not have a way to justify a reasonable yield, the best way to make sure that you can get your tapeout success is to build in a lot of margins. That’s why the more advanced technology nodes don’t give what Moore’s Law predicted: because we have to design in a lot of margin to deal with the process variation,” Liu said. Never fear, the “secrets” will be revealed in June. I hope to see you there. 

Join The ConFab discussion

The ConFab is Solid State Technology's annual conference and networking event. This year, it will be held June 23-26 at The Encore at The Wynn in Las Vegas. We recently started a LinkedIn group, where we will inform members of new activities, and keep the discussion going on topics related to semiconductor manufacturing, design, packaging and testing. Everyone is welcome to join.

The overall theme of this year’s conference is “Filling the fabs of the future,” with a focus on the types of products that will drive demand for semiconductors in the next decade, the technologies and processes that will be required to meet this demand, and the manufacturing and operational challenges that will arise as a result of this demand and how to meet them.

We’ll kick things off on Tuesday morning with a keynote talk by Yoonwoo Lee, executive advisor (and former CEO) of Samsung Electronics. He will speak on “Technologies and Business Strategies of the Future IT Industry.” Mr. Lee is well known for his accomplishments in pioneering the development of the memory chip and LCD industries in Korea, and has been widely credited for turning Samsung Electronics into a global leader in the semiconductor business.
Session 1 will focus on major economic trends, with talks from Jim Feldhan of Semico, Bill McClean of IC Insights, Mark Thirsk of Linx Consulting and Dan Hutcheson of VLSI Research.

Next, we’ll look at the design/manufacturing/packaging/testing supply chain, including collaboration between fabless/product design companies and foundries. Mike Campbell of Qualcomm and Jae Cho of Xilinx will present in this session.

In the afternoon on Monday, we’ll hear from a panel of experts on 3D integration, including Mike Ma of SiliconWare, Subu Iyer of IBM (who will also be keynoting on Tuesday morning), HoMing Tong of ASE, and Bob Patti of Terazzon. A special thanks to Phil Garrou and IEEE CPMT, the technical sponsor of this session and another session on Advanced Packaging.

Tuesday will begin with a keynote from Subu Iyer, followed by a panel session moderated by Scott Jones of Alix Partners. The session will focus on R&D Portfolio Management and Improving R&D Efficiency. Jones will share the results of a AlixPartners’ study of the 72 largest semiconductor companies globally over the past six years that found that companies with a higher degree of R&D efficiency show greater profitability.

We’ll then get into a status report on advanced packaging, with an excellent line-up of speakers, including: Devan Iyer from Texas Instruments, Bob Lanzone from Amkor, Steve Anderson from STATS ChipPAC, and Ted Tessier from FlipChip International.

In the afternoon on Tuesday, we’ll hear from Sanjay Rajguru of ISMI and a panel if speakers assembled by ISMI, focusing on accelerating manufacturing productivity.

We're posting information on the site about the speakers and their talks as we get them. Check it out!

Questions and answers on FD-SOI

A month or so ago, we implemented (without much fanfare) the ability to comment and rank articles on this site, and more easily use social media tools. I’d like to call your attention to one interesting exchange, and also invite you to start posting comments of your own.


In mid-December, we posted an article titled “STMicro: 28nm FD-SOI is ready for manufacturing” which elicited an interesting comment and response. The story noted that ST’s "feature-complete and silicon-verified" 28nm planar FD-SOI Technology Platform, which is now open for preproduction from the Crolles 300mm manufacturing facility, encompasses a full set of foundation libraries (std-cells, memory generators, I/Os, AMS IPs, and high speed interfaces), and a design flow ideally suited for developing high-speed and energy-efficient devices. Measurements on a multi-core subsystem in an ST-Ericsson NovaThor ModAp platform revealed a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V, according to Jean-Marc Chery, EVP/GM, digital sector, and CTO/chief manufacturing officer of STMicroelectronics.

Sang Kim first commented, noting that “IBM had developed FD-SOI technology for the first time, but was not successful in manufacturing up to now because of the following four main reasons: Floating body effect, self-heating, ultra-thin SOI approximately 7nm required for 28nm node, and high SOI wafer costs.” Kim noted that STMicro didn’t mention how it has resolved these four problems.

In response, STMicro’s Giorgio Cesana, director of technology marketing, posted a follow-on comment that I thought was quite interesting. Here’s what he said:

“Thank you for those comprehensive questions. Responding gives us a chance to provide details of the advances of UTBB FD-SOI technology and remove any doubts you may still have about it.

1. Ultra-Thin Body and Buried Oxide (UTBB) FD-SOI technology is very different from Partially-Depleted technologies manufactured before. Those partially-depleted technologies were affected by floating-body effects where the body was subject to an uncontrolled charging/discharging that led transistor behavior to depend on the previous transitions –i.e. making them suffer from a kind of memory effect. In UTBB FD-SOI technology, hybridation lets us contact the body, so it is not left floating, overcoming the problems with PD-SOI technologies.

2. Self-heating is also a problem that exists with partially-depleted SOI technologies, where the buried oxide thickness (~150nm) was thermally isolating transistors from the substrate, leading to self-heating effects. UTBB FD-SOI technology offers two advantages to overcome this self-heating: The Buried Oxide (BOX) is extremely thin (only 25nm thick in 28nm technology), offering significantly less thermal resistance; The big diodes, the drift MOS, the vertical bipolar, some resistors… are all implemented on the “hybrid” bulk part, eliminating even the thin BOX below them.

3. Wafer thickness: The ST process specification is for wafers with 12nm thick silicon (+/- 5A). Process manufacturing then “uses” part of the silicon film for the manufacturing of the transistors, leading to a final 7nm film below the transistors.

4. Wafer costs: UTBB FD-SOI technology manufacturing uses up to 15% fewer steps vs. our bulk planar 28LP HKMG gate-first technology. This process simplification, by itself, is capable of totally compensating for the current substrate cost difference. Then, we expect in high volume production, UTBB FD-SOI die costs should be even better than bulk planar, with substrate-cost erosion and with UTBB FD-SOI improving electrical yield over bulk planar.

We hope these answers convince you, as they’ve convinced us, of the suitability of FD-SOI technology for sub30nm semiconductor manufacturing.”

Thanks for the comments, and stay tuned for more of FD-SOI.

Present your ideas at The ConFab in 2013

The ConFab is now accepting abstract submissions for our 2013 conference, to be held June 23-26 in Las Vegas. If you’re an executive at a leading semiconductor manufacturer and would like to present at The ConFab and participate in three days of productive meetings and roundtable discussions, we’d like to hear from you!


We’re presently recruiting speakers for the following topics:

• Economic outlook of the semiconductor and related industries

• The economics of semiconductor manufacturing

• Technology trends in the semiconductor industry

• Trends in 3D Integration, TSVs, advanced packaging

• Tips on managing 150mm and 200mm legacy fabs

• Collaboration between fabless companies and foundries, particularly

success stories

• Trends in logic, memory, analog and mixed signal devices and how they

drive manufacturing requirements

• New applications for semiconductors and related devices

Please submit your abstract before December 14, 2012.

Click here to submit your abstract on-line.

Speaker/Presenter Benefits:

• Attend a high-level conference including meals, networking events and

roundtable discussions

• Opportunity to collaborate with materials suppliers as well as OEM, fab,

fabless and foundry manufacturers

• Platform to present a unique perspective on a topic of interest to

high-level executives

Please note: By submitting your abstract, you are indicating your willingness to attend and present a paper at The ConFab 2013, if selected. Please ensure that the speaker and author details you provide when submitting your abstract are correct, as these will be used for pre-event marketing purposes.

I look forward to reviewing your abstracts.

Pete Singer

The ConFab 2013 countdown begins

The countdown to The ConFab has officially begun. The dates are set: next year’s event will be held June 23-26, 2013 and we’ll be back at the Encore at The Wynn Las Vegas (an encore at The Encore!). Thanks to everyone who participated last year. We had two great keynotes – John Chen from Nvidia and Ali Sebt from Renesas – plus six other sessions, packed with great speakers. We also had our first “executive roundtable” discussion. See our recently posted "The ConFab 2012: A retrospective" for an overview of our coverage.


We’re already gearing up for next year’s event, and would like to welcome to our newest member of the advisory board, Liam Madden of Xilinx, Inc. Liam is corporate vice president of FPGA Development and Silicon Technology at Xilinx. He has responsibility for FPGA design, Advanced Packaging (including Stacked Silicon Interconnect) and Foundry Technology.

Liam joined Xilinx in 2008, bringing more than 25 years experience in a range of design and technology leadership positions with Digital Equipment Corp., MIPS Technologies, Inc., Microsoft Corp. (XBOX Division), and AMD. Liam earned a BE from the University College Dublin and a MEng from Cornell University. He holds five patents in the area of technology and circuit design.

Xilinx has been well represented at The ConFab in recent years, with Ivo Bolsens, CTO, speaking in 2011, and, in 2012, Xin Wu, Senior Director, Silicon Technology, and Sandeep Bharathi, Vice President of Engineering.

Liam joins representatives of two of the other major fabless companies already on the advisory board: Geoffrey Yeap, VP of Technology, Qualcomm Inc., and Abraham Yee, Director Advanced Technology & Package Development, Nvidia Corporation.

The ConFab is one of the few events that specifically addresses the growing importance of the fabless-foundry supply chain, and that emphasis will continue in 2013.

If you are a senior executive from the device manufacturing, foundry, packaging or fabless community, then you have the opportunity to attend The ConFab as our complimentary VIP Guest. Simply register on The ConFab website and we'll review and get back to you shortly.

For sponsorship opportunities, please contact Sabrina Straub: sabrinas@pennwell.com.

We'll be working on content shortly, so stay tuned!

Pete Singer (peters@pennwell.com).

The ConFab: Big data is here

Sponsors and delegates arrived today in sunny Las Vegas, for the 8th annual "The ConFab," our conference and networking event that features planned meetings between conference sessions. Everything is set up and we're ready to go, comfortably ensconced in The Encore at The Wynn. The conference and meals will be in the Bach and Beethoven rooms on the second floor (very nice!) and we have a networking reception event tonight at Brahms on the first floor, which has an indoor area and an outdoor patio near the pool area.


I ran into some colleagues almost as soon as I arrived, and we had a nice lunch at the Society Café (crab salad for me). After we all compared our smart phones (one iphone, two Androids and one Windows phone), we talked about how the semiconductor industry has changed over the years. One interesting tidbit was that a member of our group had heard that over 90% of the world’s data has been created in the last two years (I found out later that this factoid comes from IBM in a report on so-called "big data").

What is big data? According to IBM, every day, we create 2.5 quintillion bytes of data — so much that 90% of the data in the world today has been created in the last two years alone. This data comes from everywhere: sensors used to gather climate information, posts to social media sites, digital pictures and videos, purchase transaction records, and cell phone GPS signals to name a few. Big data is any type of data - structured and unstructured data such as text, sensor data, audio, video, click streams, log files and more. New insights are found when analyzing these data types together.

The concept of big data isn’t that new – in fact it's one of the trendy buzz works in business-to-business media today, and was a focal point of this year's American Business Media’s annual conference. In a presentation titled “Building the Big Data-Driven Media Company of the Future,” Frank Cutitta, CEO, The Center for Global Branding discussed how an "integrated database can help companies streamline their customers' experience, uncover new product opportunities and execute a successful lead generation program. But most importantly, it can give b-to-b media companies a chance to target customers based on their preferences." Yes, people are working on that at PennWell, but I digress.

Just imagine what this will mean for the semiconductor industry. Massive amounts of data are already being generated, and the future of many businesses will hinge on how quickly that data is collected and analyzed. Cha-ching! IBM says volume, velocity and variety will be key: Enterprises are awash with ever-growing data of all types, easily amassing terabytes—even petabytes—of information. "How do you turn 12 terabytes of Tweets created each day into improved product sentiment analysis?" they ask.

That's just one of the thoughts from The ConFab this year. More than 90% of the world's data has been generated in the last two years. Mind-boggling!!

Another thought – if you're not here, you're really missing out!

Oh, snap!: Pics from The ConFab

Some pics from The ConFab 2012 setup:

Getting the conference books ready to distribute (Luba and Karen), inside the book, various signs -- sessions, sponsors, Solid State Technology -- view down the hall, Sabrina at the conference table, The ConFab map.