Join The ConFab discussion

The ConFab is Solid State Technology's annual conference and networking event. This year, it will be held June 23-26 at The Encore at The Wynn in Las Vegas. We recently started a LinkedIn group, where we will inform members of new activities, and keep the discussion going on topics related to semiconductor manufacturing, design, packaging and testing. Everyone is welcome to join.

The overall theme of this year’s conference is “Filling the fabs of the future,” with a focus on the types of products that will drive demand for semiconductors in the next decade, the technologies and processes that will be required to meet this demand, and the manufacturing and operational challenges that will arise as a result of this demand and how to meet them.

We’ll kick things off on Tuesday morning with a keynote talk by Yoonwoo Lee, executive advisor (and former CEO) of Samsung Electronics. He will speak on “Technologies and Business Strategies of the Future IT Industry.” Mr. Lee is well known for his accomplishments in pioneering the development of the memory chip and LCD industries in Korea, and has been widely credited for turning Samsung Electronics into a global leader in the semiconductor business.
Session 1 will focus on major economic trends, with talks from Jim Feldhan of Semico, Bill McClean of IC Insights, Mark Thirsk of Linx Consulting and Dan Hutcheson of VLSI Research.

Next, we’ll look at the design/manufacturing/packaging/testing supply chain, including collaboration between fabless/product design companies and foundries. Mike Campbell of Qualcomm and Jae Cho of Xilinx will present in this session.

In the afternoon on Monday, we’ll hear from a panel of experts on 3D integration, including Mike Ma of SiliconWare, Subu Iyer of IBM (who will also be keynoting on Tuesday morning), HoMing Tong of ASE, and Bob Patti of Terazzon. A special thanks to Phil Garrou and IEEE CPMT, the technical sponsor of this session and another session on Advanced Packaging.

Tuesday will begin with a keynote from Subu Iyer, followed by a panel session moderated by Scott Jones of Alix Partners. The session will focus on R&D Portfolio Management and Improving R&D Efficiency. Jones will share the results of a AlixPartners’ study of the 72 largest semiconductor companies globally over the past six years that found that companies with a higher degree of R&D efficiency show greater profitability.

We’ll then get into a status report on advanced packaging, with an excellent line-up of speakers, including: Devan Iyer from Texas Instruments, Bob Lanzone from Amkor, Steve Anderson from STATS ChipPAC, and Ted Tessier from FlipChip International.

In the afternoon on Tuesday, we’ll hear from Sanjay Rajguru of ISMI and a panel if speakers assembled by ISMI, focusing on accelerating manufacturing productivity.

We're posting information on the site about the speakers and their talks as we get them. Check it out!

Questions and answers on FD-SOI

A month or so ago, we implemented (without much fanfare) the ability to comment and rank articles on this site, and more easily use social media tools. I’d like to call your attention to one interesting exchange, and also invite you to start posting comments of your own.


In mid-December, we posted an article titled “STMicro: 28nm FD-SOI is ready for manufacturing” which elicited an interesting comment and response. The story noted that ST’s "feature-complete and silicon-verified" 28nm planar FD-SOI Technology Platform, which is now open for preproduction from the Crolles 300mm manufacturing facility, encompasses a full set of foundation libraries (std-cells, memory generators, I/Os, AMS IPs, and high speed interfaces), and a design flow ideally suited for developing high-speed and energy-efficient devices. Measurements on a multi-core subsystem in an ST-Ericsson NovaThor ModAp platform revealed a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V, according to Jean-Marc Chery, EVP/GM, digital sector, and CTO/chief manufacturing officer of STMicroelectronics.

Sang Kim first commented, noting that “IBM had developed FD-SOI technology for the first time, but was not successful in manufacturing up to now because of the following four main reasons: Floating body effect, self-heating, ultra-thin SOI approximately 7nm required for 28nm node, and high SOI wafer costs.” Kim noted that STMicro didn’t mention how it has resolved these four problems.

In response, STMicro’s Giorgio Cesana, director of technology marketing, posted a follow-on comment that I thought was quite interesting. Here’s what he said:

“Thank you for those comprehensive questions. Responding gives us a chance to provide details of the advances of UTBB FD-SOI technology and remove any doubts you may still have about it.

1. Ultra-Thin Body and Buried Oxide (UTBB) FD-SOI technology is very different from Partially-Depleted technologies manufactured before. Those partially-depleted technologies were affected by floating-body effects where the body was subject to an uncontrolled charging/discharging that led transistor behavior to depend on the previous transitions –i.e. making them suffer from a kind of memory effect. In UTBB FD-SOI technology, hybridation lets us contact the body, so it is not left floating, overcoming the problems with PD-SOI technologies.

2. Self-heating is also a problem that exists with partially-depleted SOI technologies, where the buried oxide thickness (~150nm) was thermally isolating transistors from the substrate, leading to self-heating effects. UTBB FD-SOI technology offers two advantages to overcome this self-heating: The Buried Oxide (BOX) is extremely thin (only 25nm thick in 28nm technology), offering significantly less thermal resistance; The big diodes, the drift MOS, the vertical bipolar, some resistors… are all implemented on the “hybrid” bulk part, eliminating even the thin BOX below them.

3. Wafer thickness: The ST process specification is for wafers with 12nm thick silicon (+/- 5A). Process manufacturing then “uses” part of the silicon film for the manufacturing of the transistors, leading to a final 7nm film below the transistors.

4. Wafer costs: UTBB FD-SOI technology manufacturing uses up to 15% fewer steps vs. our bulk planar 28LP HKMG gate-first technology. This process simplification, by itself, is capable of totally compensating for the current substrate cost difference. Then, we expect in high volume production, UTBB FD-SOI die costs should be even better than bulk planar, with substrate-cost erosion and with UTBB FD-SOI improving electrical yield over bulk planar.

We hope these answers convince you, as they’ve convinced us, of the suitability of FD-SOI technology for sub30nm semiconductor manufacturing.”

Thanks for the comments, and stay tuned for more of FD-SOI.

Present your ideas at The ConFab in 2013

The ConFab is now accepting abstract submissions for our 2013 conference, to be held June 23-26 in Las Vegas. If you’re an executive at a leading semiconductor manufacturer and would like to present at The ConFab and participate in three days of productive meetings and roundtable discussions, we’d like to hear from you!


We’re presently recruiting speakers for the following topics:

• Economic outlook of the semiconductor and related industries

• The economics of semiconductor manufacturing

• Technology trends in the semiconductor industry

• Trends in 3D Integration, TSVs, advanced packaging

• Tips on managing 150mm and 200mm legacy fabs

• Collaboration between fabless companies and foundries, particularly

success stories

• Trends in logic, memory, analog and mixed signal devices and how they

drive manufacturing requirements

• New applications for semiconductors and related devices

Please submit your abstract before December 14, 2012.

Click here to submit your abstract on-line.

Speaker/Presenter Benefits:

• Attend a high-level conference including meals, networking events and

roundtable discussions

• Opportunity to collaborate with materials suppliers as well as OEM, fab,

fabless and foundry manufacturers

• Platform to present a unique perspective on a topic of interest to

high-level executives

Please note: By submitting your abstract, you are indicating your willingness to attend and present a paper at The ConFab 2013, if selected. Please ensure that the speaker and author details you provide when submitting your abstract are correct, as these will be used for pre-event marketing purposes.

I look forward to reviewing your abstracts.

Pete Singer

The ConFab 2013 countdown begins

The countdown to The ConFab has officially begun. The dates are set: next year’s event will be held June 23-26, 2013 and we’ll be back at the Encore at The Wynn Las Vegas (an encore at The Encore!). Thanks to everyone who participated last year. We had two great keynotes – John Chen from Nvidia and Ali Sebt from Renesas – plus six other sessions, packed with great speakers. We also had our first “executive roundtable” discussion. See our recently posted "The ConFab 2012: A retrospective" for an overview of our coverage.


We’re already gearing up for next year’s event, and would like to welcome to our newest member of the advisory board, Liam Madden of Xilinx, Inc. Liam is corporate vice president of FPGA Development and Silicon Technology at Xilinx. He has responsibility for FPGA design, Advanced Packaging (including Stacked Silicon Interconnect) and Foundry Technology.

Liam joined Xilinx in 2008, bringing more than 25 years experience in a range of design and technology leadership positions with Digital Equipment Corp., MIPS Technologies, Inc., Microsoft Corp. (XBOX Division), and AMD. Liam earned a BE from the University College Dublin and a MEng from Cornell University. He holds five patents in the area of technology and circuit design.

Xilinx has been well represented at The ConFab in recent years, with Ivo Bolsens, CTO, speaking in 2011, and, in 2012, Xin Wu, Senior Director, Silicon Technology, and Sandeep Bharathi, Vice President of Engineering.

Liam joins representatives of two of the other major fabless companies already on the advisory board: Geoffrey Yeap, VP of Technology, Qualcomm Inc., and Abraham Yee, Director Advanced Technology & Package Development, Nvidia Corporation.

The ConFab is one of the few events that specifically addresses the growing importance of the fabless-foundry supply chain, and that emphasis will continue in 2013.

If you are a senior executive from the device manufacturing, foundry, packaging or fabless community, then you have the opportunity to attend The ConFab as our complimentary VIP Guest. Simply register on The ConFab website and we'll review and get back to you shortly.

For sponsorship opportunities, please contact Sabrina Straub: sabrinas@pennwell.com.

We'll be working on content shortly, so stay tuned!

Pete Singer (peters@pennwell.com).

The ConFab: Big data is here

Sponsors and delegates arrived today in sunny Las Vegas, for the 8th annual "The ConFab," our conference and networking event that features planned meetings between conference sessions. Everything is set up and we're ready to go, comfortably ensconced in The Encore at The Wynn. The conference and meals will be in the Bach and Beethoven rooms on the second floor (very nice!) and we have a networking reception event tonight at Brahms on the first floor, which has an indoor area and an outdoor patio near the pool area.


I ran into some colleagues almost as soon as I arrived, and we had a nice lunch at the Society Café (crab salad for me). After we all compared our smart phones (one iphone, two Androids and one Windows phone), we talked about how the semiconductor industry has changed over the years. One interesting tidbit was that a member of our group had heard that over 90% of the world’s data has been created in the last two years (I found out later that this factoid comes from IBM in a report on so-called "big data").

What is big data? According to IBM, every day, we create 2.5 quintillion bytes of data — so much that 90% of the data in the world today has been created in the last two years alone. This data comes from everywhere: sensors used to gather climate information, posts to social media sites, digital pictures and videos, purchase transaction records, and cell phone GPS signals to name a few. Big data is any type of data - structured and unstructured data such as text, sensor data, audio, video, click streams, log files and more. New insights are found when analyzing these data types together.

The concept of big data isn’t that new – in fact it's one of the trendy buzz works in business-to-business media today, and was a focal point of this year's American Business Media’s annual conference. In a presentation titled “Building the Big Data-Driven Media Company of the Future,” Frank Cutitta, CEO, The Center for Global Branding discussed how an "integrated database can help companies streamline their customers' experience, uncover new product opportunities and execute a successful lead generation program. But most importantly, it can give b-to-b media companies a chance to target customers based on their preferences." Yes, people are working on that at PennWell, but I digress.

Just imagine what this will mean for the semiconductor industry. Massive amounts of data are already being generated, and the future of many businesses will hinge on how quickly that data is collected and analyzed. Cha-ching! IBM says volume, velocity and variety will be key: Enterprises are awash with ever-growing data of all types, easily amassing terabytes—even petabytes—of information. "How do you turn 12 terabytes of Tweets created each day into improved product sentiment analysis?" they ask.

That's just one of the thoughts from The ConFab this year. More than 90% of the world's data has been generated in the last two years. Mind-boggling!!

Another thought – if you're not here, you're really missing out!

Oh, snap!: Pics from The ConFab

Some pics from The ConFab 2012 setup:

Getting the conference books ready to distribute (Luba and Karen), inside the book, various signs -- sessions, sponsors, Solid State Technology -- view down the hall, Sabrina at the conference table, The ConFab map.

Funding the future: How best to spend limited R&D dollars?

One of the big issues now facing the industry is to how best spend limited funding for research and development, when so much needs to be done. Continued scaling to 20nm and below, a transition to 450mm, 3D integration, device new structures, a bevy of new materials with unknown integration challenges - these are all needed.

These issues are top of mind since I've been asked to moderate a panel on this topic at the upcoming Advanced Semiconductor Manufacturing Conference (ASMC), to be held May 15-18 in Saratoga Springs, NY. The panel, "Competing for R&D Dollars: Funding the Future," will be held on May 16, 2012 from 4:30 to 5:45. The panelists will be:

-- David Bennett, VP Alliances, GLOBALFOUNDRIES;
-- Noreen Harned, VP Marketing, ASML;
-- Subramanian (Subu) Iyer, IBM Fellow, IBM Systems & Technology Group;
-- Nag Patibandla, Sr. Director (Office of CTO), Applied Materials; and
-- Risto Puhakka, President, VLSI Research.

Each panelist will give a brief overview of their perspective on the topic with no more than two slides, and then we'll move into the panel discussion.

I think it's fairly clear that, with the industry's present model, it's going to be difficult to fully finance everything on the wish list. In fact, that's been one of the main arguments against going to 450mm: Wouldn't precious R&D dollars (or euros/yens/RMBs) be better spent on some other endeavor, such as 3D integration?

This isn't a new dilemma, of course. In a SEMI-funded reported published in 2005, Ron Leckie analyzed all the things that were noted in the International Technology Roadmap for Semiconductors (ITRS) and concluded that the funding gap could reach upwards of $9.3 billion by 2010. It's now 2012 and, two years later, Moore's Law is holding firm. On the other hand, there has been a fair amount of consolidation, and a shift to fabless and asset-lite (or capital-lite) business models.

In this blog, over two years ago, I reported that some believed that a massive restructuring is underway that will leave only a handful of companies producing devices at the leading edge. Bob Johnson, VP of research at Gartner, predicts that by 2014 there will be only 10 companies operating at the leading edge: 1-2 non-memory IDMs, 4-5 memory companies, and 3 foundries (speaking at SEMI's 2010 ISS). I haven't seen much to contradict that thinking. The percentage of revenue that chip makers are spending on R&D is fairly low, around 14%. It was at a historical low in 2010, only 12%

The way the industry has been able to get around the funding challenge is through collaboration. Consortia such as SEMATECH and imec are great models of collaboration, enabling companies to work on "pre-competitive" research to share costs and reduce risks. The Common Platform model employed by IBM/Samsung/GLOBALFOUNDRIES is another great example of collaboration. The entire CNSE/Albany Nanotech/G450C effort is perhaps the best example of university, industry, consortia and government working together (as I'm sure will be discussed at ASMC).

What's intriguing to me, though, is if the semiconductor industry will go the way of the automotive and aerospace industries, which have very different models when it comes to cost-sharing and risk-sharing. Mike Splinter of Applied Materials, Steve Newberry of Lam and Paolo Gargini of Intel all made references to those models at this year's ISS.

I don't have the answers, but if you have questions you'd like to pose to the ASMC panel, and aren't going to make it in person, let me know: peters@pennwell.com.