Tuesday, September 3, 2013

How to Contribute to SST

One of the most common questions I’m asked is “How can I contribute to Solid State Technology?” We try to make that an easy process – so the short answer is shoot me an e-mail (psinger@extensionmedia.com) or give me a call (978-470-1806) – but I prepared this short guide as an overview of the different ways to contribute.  

First, a little about us: Solid State Technology is a trusted source of technology, product and market information on semiconductor manufacturing and packaging since 1958. Our coverage also includes growth and emerging electronics technologies and markets, including MEMS, LEDs, displays, power electronics and bio-medical devices.

How many people do we reach? Solid State Technology’s magazine, email newsletters and website are seen by more than 273,000 engineering and management professionals in 181 countries each month—more than any other electronics manufacturing-focused media provider delivers. We provide news and product information on a daily basis in combination with in-depth technical articles, analysis and case studies.

Here's our line-up of publications:
·        sMagazine: Leading-edge and strategic articles and commentary delivered eight times a year to 40,000 of the most qualified decision makers for semiconductor, packaging, MEMS, LED and display manufacturing worldwide, plus attendees of key conferences and trade shows;
·         Email Newsletters: Dedicated e-newsletters focus on each of these key market segments, with circulations ranging from 10,000 to 45,000 subscribers, and a daily roundup provides the latest news and product announcements across all of these industries;
·         Website: Dedicated channels on the www.solid-state.com site focus on our five key microelectronics manufacturing coverage areas—semiconductors, packaging, MEMS, LEDs and displays—providing news, technical articles, product updates, blogs, webcasts, podcasts, white papers, video, an extensive buyer’s guide and much more;
·         Events: One of the key events of the year, The ConFab is an annual invitation-only conference that gathers the leaders who will determine the future of the industry.

There are a number of ways in which you can work with Solid State Technology.

Feature Articles

Solid State Technology publishes feature-length articles in our magazine and on our website, and we do accept contributed articles. We welcome suggestions for articles of all types, including application stories and case studies; technical articles and reviews; and conference/trade-show reports.
Our typical article length is 1500-2000 words. We also publish opinion pieces in our Industry Forum column which are 600 words in length.

Please send us a short summary of the proposed content (100-150 words), so that we can discuss publishing options.

Please review our Editorial Policy and our guidelines for submitting material (see below).

News Stories and New Products

News items are published on a daily basis on our website (www.solid-state.com). News items are also included in our various newsletters and in the magazine. Send your press releases regarding news or new products to Shannon Davis, digital media editor (shannond@extensionmedia.com).


For those interested in ongoing, regular contributed, a blog might be the way to go. Please send me the proposed title of the blog and what you intend to cover, and we can get the conversation started (psinger@extensionmedia.com). 

White Papers 

White Papers are technical articles describing your company's products, their applications, and capabilities. These articles are published on our website at and promoted via our newsletters. Companies supply a PDF version of their article, which is posted on the Solid State Technology website. Readers sign in to download the PDF. Reader details are gathered and supplied to companies on a monthly basis, providing a useful lead generation tool.  The paper is promoted to readers via our website and via our email newsletters.

Buyer's Guide and Directory
You can list your company's details in our online Buyer's Guide, which provides year-round 24/7 exposure on our website. Basic listings are FREE, and we also offer various paid-for options to enhance your company’s profile
Buyer’s Guide: http://buyersguide.electroiq.com/search/index.html

Solid State Technology’s Editorial Policy

We are happy to discuss all potential articles related to the manufacturing and packaging of semiconductors and other types of electronics, particularly MEMS, LEDs, displays and power electronics.

We publish technical articles, case studies, application notes, product information, business and financial news, and a wide variety of other information relevant to the industries we cover.
We are looking for original material that has not been published elsewhere (e.g. other trade publications or on the author’s website), although material based on peer-reviewed journals or conference seminars is often acceptable.

Please do not submit articles where the primary purpose is to promote your company and its products. Readers do not respond well to such marketing pieces. We have many (paid-for) ways to help you put across your marketing message.

Typical articles could address a specific challenge or need within the industry, or look at the merits of using new process technology in a particular application, or discuss new standards, policies or collaborative projects.

Submitting proposals:

The best first step is to send me a short 100-150 word summary of the proposed article. Although we publish a limited Editorial Calendar in our Media Planner, we are happy to discuss all subject matter, whether or not it appears on the Calendar.


We work around 3 months ahead of publication. Submission deadlines are 3 weeks prior to the advertising sales deadlines published in our Media Planner (http://www.electroiq.com/advertise.html).

All articles will be edited according to our internal procedures. Any major queries or problems will be returned to the author.

Please send proposal for features, columns and blogs to Pete Singer, Editor-in-Chief (peters@extensionmedia.com).

Thanks for the interest and I look forward to working with you.

Pete Singer

Friday, July 19, 2013

Key Trends at Semicon West 2013

At Semicon West last week (and at The ConFab a few weeks ago) some key trends were clearly evident in the semiconductor industry. 

It’s apparent that the world’s appetite for electronics has never been greater. That has increasingly taken the form of mobile electronics, including smartphones, tablets and tablets and the new “phablets.” People want to watch movies and live sports on their phones. They want their mobile devices to be “situationally aware” and even capable of monitoring their health through sensors. That drives higher bandwidth (6G is on the drawing board), faster data rates and a demand for reduced power consumption to conserve battery life. At the same time, “big data” and the internet of things (IoT) are here, which drives the demand for server networks and high performance semiconductors, as well as integrated sensors and inventive gadgets such as flexible displays and human biosensor networks.

It’s also pushing the semiconductor manufacturing industry in new directions. Chip makers typically face tradeoffs between power, performance, area and cost/complexity (PPAC). For mobile devices, the push is to low power, high performance, small area and low cost.
For me, one of the main themes of Semicon West was the demand for mobile devices and how they might impact what has become standard thinking in the semiconductor industry in terms of scaling, performance, power and cost.

At Semicon West 2013, Karen Savala, president of SEMI Americas, kicked things off, noting that it was the 43rd year of Semicon West (32nd consecutive one for me personally). “While much has changed over the years, the one that has been constant is the power of our industry to continually drive innovation, to overcome technical challenges and economic challenges, and develop new processes, new materials and technologies that continue to move Moore’s Law forward,” Savala said. “2013 is no different. The industry finds itself at a critical juncture where multiple technology developments, including 450mm, FinFETs, 3D ICs, advanced materials and processes, and EUV just to name a few, promise to move Moore’s Law ahead. But as we have done before, we will address these challenges, bring new technologies to market, and continue to amaze the world with the power of our collective innovation.”

Karen then introducde the keynote, Ajit Monacha, CEO of Global Foundries, who expanded on his Foundry 2.0 concept, and talked about how the requirements of mobile devices were, in fact, changing the entire semiconductor industry. He noted that the mobile business is forecast to be double the size of the PC market in 2016. The mobile business drives many new requirements, said Manocha, including power, performance and features, higher data rates, high resolution multicore processors and thinner form factors.

This incredible growth is driving new dynamics, said Manocha, and pushing the industry to the new technology node each year, which is presenting the industry with what Manocha deems the Big Five Challenges. Manocha believes these challenges are: cost, device architectures, lithography and EUV, packaging and the 450mm wafer transition. I don’t recall when cost wasn’t an issue, but an audience poll revealed that most people believe economic challenges will be the main factor limiting industry growth, not technical challenges, so cost moves to the top of the list.

After his talk, Ajit was presented with the “SEMI Outstanding EHS Achievement Award — Inspired by Akira Inoue” by Denny McGuirk, president and CEO of SEMI. During Semicon West, SEMI also honored 14 industry leaders for their outstanding accomplishments in developing standards for the microelectronics and related industries

Part of “the buzz” at the show was the rosy prediction issued by SEMI about growth in capital equipment for next year. SEMI forecasts semiconductor equipment sales will reach $43.98 billion in 2014, a 21 percent increase over estimated 2013 equipment spending, according to the mid-year edition of the SEMI Capital Equipment Forecast, released during the show.

Lots more to cover, so stay tuned. In the meantime, check out our other coverage of Semicon West at our dedicated landing page.

Wednesday, May 22, 2013

Tackling Design for Yield Questions at DAC

Process variations are unavoidable, but how can chip designers plan for them in their designs to obtain optimal yield and device performance? That’s one of the focal points of a pavilion panel at the upcoming Design Automation Conference (DAC), to be held June 2-6 in Austin, TX. Titled "Learn the Secrets of Design for Yield," it will be moderated by yours truly with panelists: Shaofeng Yu of Semiconductor Manufacturing International (SMIC); Dr. Min-Chie Jeng from Taiwan Semiconductor Manufacturing Co. (TSMC); and Dr. Luigi Capodieci from GLOBALFOUNDRIES.

Time and place: Wednesday, June 5th, from 1:30 to 2:15 pm, Booth #509 on the DAC exhibit floor.

Foundries supply process information to chip designers, but according to Dr. Zhihong Liu, CEO of ProPlus Design Solutions (one of the organizers of the session), this process information is sometimes either too conservative or too optimistic, and the foundry models may be used inappropriately or incorrectly on an application-specific basis. Compounding the problem are selective corner models (i.e., process, voltage and temperature or “PVT” corners) and Monte Carlo analysis approaches often employed by circuit designers may give limited information, giving them low confidence on the yield prediction and design optimization.

The panel will look at advanced process node challenges that highlight increased random process variations and layout-dependent effects designers must address in SoC design. The panel of foundry experts will share techniques to manage these sub-nanometer effects to improve manufacturability and yield.

Liu said Monte Carlo analysis works well, but can be costly because it takes so long to run. In the past, designers have used Monte Carlo analysis for some key components, but now it will be required more often for “all kinds of circuits and components,” Liu said. He added that there are some tricks you can use to ease the pain of Monte Carlo simulation, such as parallelization and advanced algorithms. “People generally use so-called advanced sampling technology. That is a sort of statistical algorithm, trying to not reduce the accuracy of the simulation in terms of statistics, yet still significantly reduce the sampling size so that you don’t need to simulate a thousand or million of times, Liu said.

Design for Yield (DFY) has quite a different meaning to the chip design industry than Design for Manufacturing (DFM). DFM was a common buzzword in the 2004-2005 timeframe, although everyone seemed to define it a bit differently. EDA suppliers eventually came up with a commercial DFM solution, after which the term DFM fell out of favor. DFY today refers to the gap between what the designers think they need to guarantee a reliable design and what the manufacturer or foundry think they need from the designers to be able to manufacture the product in a reliable fashion.

SoCs are clearly getting bigger and more complex. At the Advanced Semiconductor Manufacturing Conference in May, Subi Kengeri, vp of advanced technology architecture at GLOBALFOUNDRIES, said 47% of SoC designs now use more than 5M gates. There are also a larger number of clock domains, which means managing multiple macros operating at different frequencies. There are also more voltage domains across the chip, with five now being the average.

Among the question the DFY DAC panel will address: How do foundries handle variability analysis? What are the conditions for tapeout? Can designers trust the foundry models? Do they need to run Monte Carlo analysis (and if so, how can they speed it up?). How many PVT corners do they need to verify?

Liu says that designers need to have support from CAD vendors, and also they need to have the model variation information from foundries. “If those are well integrated with a reasonable efficiency, the design job will be more suitable for higher yield or a better tradeoff between yield and performance,” he said. If that doesn’t exist (and it often doesn’t) bad things can happen. “Sometimes, if you do not have a way to justify a reasonable yield, the best way to make sure that you can get your tapeout success is to build in a lot of margins. That’s why the more advanced technology nodes don’t give what Moore’s Law predicted: because we have to design in a lot of margin to deal with the process variation,” Liu said. Never fear, the “secrets” will be revealed in June. I hope to see you there. 

Tuesday, February 26, 2013

Join The ConFab discussion

The ConFab is Solid State Technology's annual conference and networking event. This year, it will be held June 23-26 at The Encore at The Wynn in Las Vegas. We recently started a LinkedIn group, where we will inform members of new activities, and keep the discussion going on topics related to semiconductor manufacturing, design, packaging and testing. Everyone is welcome to join.

The overall theme of this year’s conference is “Filling the fabs of the future,” with a focus on the types of products that will drive demand for semiconductors in the next decade, the technologies and processes that will be required to meet this demand, and the manufacturing and operational challenges that will arise as a result of this demand and how to meet them.

We’ll kick things off on Tuesday morning with a keynote talk by Yoonwoo Lee, executive advisor (and former CEO) of Samsung Electronics. He will speak on “Technologies and Business Strategies of the Future IT Industry.” Mr. Lee is well known for his accomplishments in pioneering the development of the memory chip and LCD industries in Korea, and has been widely credited for turning Samsung Electronics into a global leader in the semiconductor business.
Session 1 will focus on major economic trends, with talks from Jim Feldhan of Semico, Bill McClean of IC Insights, Mark Thirsk of Linx Consulting and Dan Hutcheson of VLSI Research.

Next, we’ll look at the design/manufacturing/packaging/testing supply chain, including collaboration between fabless/product design companies and foundries. Mike Campbell of Qualcomm and Jae Cho of Xilinx will present in this session.

In the afternoon on Monday, we’ll hear from a panel of experts on 3D integration, including Mike Ma of SiliconWare, Subu Iyer of IBM (who will also be keynoting on Tuesday morning), HoMing Tong of ASE, and Bob Patti of Terazzon. A special thanks to Phil Garrou and IEEE CPMT, the technical sponsor of this session and another session on Advanced Packaging.

Tuesday will begin with a keynote from Subu Iyer, followed by a panel session moderated by Scott Jones of Alix Partners. The session will focus on R&D Portfolio Management and Improving R&D Efficiency. Jones will share the results of a AlixPartners’ study of the 72 largest semiconductor companies globally over the past six years that found that companies with a higher degree of R&D efficiency show greater profitability.

We’ll then get into a status report on advanced packaging, with an excellent line-up of speakers, including: Devan Iyer from Texas Instruments, Bob Lanzone from Amkor, Steve Anderson from STATS ChipPAC, and Ted Tessier from FlipChip International.

In the afternoon on Tuesday, we’ll hear from Sanjay Rajguru of ISMI and a panel if speakers assembled by ISMI, focusing on accelerating manufacturing productivity.

We're posting information on the site about the speakers and their talks as we get them. Check it out!

Friday, January 4, 2013

Questions and answers on FD-SOI

A month or so ago, we implemented (without much fanfare) the ability to comment and rank articles on this site, and more easily use social media tools. I’d like to call your attention to one interesting exchange, and also invite you to start posting comments of your own.

In mid-December, we posted an article titled “STMicro: 28nm FD-SOI is ready for manufacturing” which elicited an interesting comment and response. The story noted that ST’s "feature-complete and silicon-verified" 28nm planar FD-SOI Technology Platform, which is now open for preproduction from the Crolles 300mm manufacturing facility, encompasses a full set of foundation libraries (std-cells, memory generators, I/Os, AMS IPs, and high speed interfaces), and a design flow ideally suited for developing high-speed and energy-efficient devices. Measurements on a multi-core subsystem in an ST-Ericsson NovaThor ModAp platform revealed a maximum frequency exceeding 2.5Ghz and delivering 800 MHz at 0.6V, according to Jean-Marc Chery, EVP/GM, digital sector, and CTO/chief manufacturing officer of STMicroelectronics.

Sang Kim first commented, noting that “IBM had developed FD-SOI technology for the first time, but was not successful in manufacturing up to now because of the following four main reasons: Floating body effect, self-heating, ultra-thin SOI approximately 7nm required for 28nm node, and high SOI wafer costs.” Kim noted that STMicro didn’t mention how it has resolved these four problems.

In response, STMicro’s Giorgio Cesana, director of technology marketing, posted a follow-on comment that I thought was quite interesting. Here’s what he said:

“Thank you for those comprehensive questions. Responding gives us a chance to provide details of the advances of UTBB FD-SOI technology and remove any doubts you may still have about it.

1. Ultra-Thin Body and Buried Oxide (UTBB) FD-SOI technology is very different from Partially-Depleted technologies manufactured before. Those partially-depleted technologies were affected by floating-body effects where the body was subject to an uncontrolled charging/discharging that led transistor behavior to depend on the previous transitions –i.e. making them suffer from a kind of memory effect. In UTBB FD-SOI technology, hybridation lets us contact the body, so it is not left floating, overcoming the problems with PD-SOI technologies.

2. Self-heating is also a problem that exists with partially-depleted SOI technologies, where the buried oxide thickness (~150nm) was thermally isolating transistors from the substrate, leading to self-heating effects. UTBB FD-SOI technology offers two advantages to overcome this self-heating: The Buried Oxide (BOX) is extremely thin (only 25nm thick in 28nm technology), offering significantly less thermal resistance; The big diodes, the drift MOS, the vertical bipolar, some resistors… are all implemented on the “hybrid” bulk part, eliminating even the thin BOX below them.

3. Wafer thickness: The ST process specification is for wafers with 12nm thick silicon (+/- 5A). Process manufacturing then “uses” part of the silicon film for the manufacturing of the transistors, leading to a final 7nm film below the transistors.

4. Wafer costs: UTBB FD-SOI technology manufacturing uses up to 15% fewer steps vs. our bulk planar 28LP HKMG gate-first technology. This process simplification, by itself, is capable of totally compensating for the current substrate cost difference. Then, we expect in high volume production, UTBB FD-SOI die costs should be even better than bulk planar, with substrate-cost erosion and with UTBB FD-SOI improving electrical yield over bulk planar.

We hope these answers convince you, as they’ve convinced us, of the suitability of FD-SOI technology for sub30nm semiconductor manufacturing.”

Thanks for the comments, and stay tuned for more of FD-SOI.