Thursday, October 29, 2009

Acro Energy Prez Defines PV User Demands

Acro Energy Technologies Corp., a leading U.S. solar integrator, announced yesterday that it has signed a Stock Purchase Agreement with Energy Efficiency Solar, Inc., a California corporation headquartered in Pomona, Calif. ("EE Solar") and Bill
Korthof, the sole shareholder of EE Solar.

EE Solar is a full-service solar energy company that has been installing residential and commercial solar systems in Los Angeles, Orange, and San Bernardino Counties since 1989. EE Solar generated approximately $4.2 million in revenue in 2008, servicing customers from its offices in Pomona and Orange. Korthof is the president of EE Solar and will join the Acro Energy team.

"Southern California is the largest growth market for distribute solar," said Nat Kreamer, President of Acro Energy. "Bill and the EE Solar team give Acro a strong platform for helping more southern Californians - who pay among the highest rates for electricity in the Country - save with solar."

Under the Purchase Agreement, Acro Energy will acquire all of the issued and outstanding shares of EE Solar for a purchase price of $1,500,000, consisting of
$250,000 cash, a promissory note in the amount of $750,000, and $500,000 of common stock issued from the treasury of the Company at a deemed price of CDN$0.24 per share. The company will also enter into an employment agreement with Korthof, as general manager, Pomona Operations.

I had the good fortune to catch up with Nat Kreamer yesterday before the deal was signed, and asked him what it was his customers were looking for in a PV system. In addition to being the interim President of Acro Energy Technologies and member of the Board of Directors, he was a founder, President, and Chief Operating Officer of SunRun, a leading provider of residential solar power purchase agreements. Kreamer has also worked in power industry consulting, clean energy investing, and energy trading. He graduated from Rice University and Northwestern University. An officer in the US Navy (Reserves), Kreamer is an Afghanistan war veteran and recipient of the Bronze Star Medal. He is a Senior Advisor at the Madison Policy Forum, which promotes non-partisan dialog about timely national security issues.

Here’s the Q&A with Kreamer:

Q: When you look at all the various elements of a PV system – the cells, inverters, cabling, trackers – where is the technology going and how aware are your customers of changes and how things are evolving? What are their main requirements?

A: Clearly we’ve seen a lot of upstream investment in the marketplace. In solar panel equipment/module manufacturers all the way to people like Spire who make the fab equipment. That has benefited the declining ASPs which really grows the addressable market of solar because it’s made it more affordable for people and more cost-competitive vis-à-vis power from the grid: the avoided cost of power. I think that general trend is very positive for the whole industry. In essence it will have a much larger industry and there will be more power generated from solar here in the United States and around the world.

There are a couple of things that an end customer thinks about. We think about it in two parts: We are an integration business at Acro, meaning we need to decide who we are going to have a relationship with from a manufacturer’s standpoint and what products we are going to install on customers roofs. Some of those customers pay us directly as cash so they’re the end consumer of the power and they also own the system. Other customers, such as SunRun, own the system and they sell electricity to the end customer. In both of those cases, clearly price is important because it needs to be economically valuable to go solar for the customer. Quality and reliability are very important. The level of service from the manufacturer is also important. You’ve got to have all three of those to be a contender with serious businesses in this industry. That can be a challenge for some of the more start-up organizations that you get in module manufacturing as well as the inverter space where you have complex, expensive pieces of equipment that are essential to the system and should have a long life. As a consequence I think end users tend to be less experimental with what they’re buying as equipment because they want to know they will get the power that they paid for, whether they are a buyer of capacity and consumer of that power or they’re a buyer of capacity and a reseller of electricity.

The one thing that you clearly see is that most manufacturers today are able to create a module on the silicon side that has enough Watts for it to work in nearly every application. So Watt-density or efficiency is less of an issue in the residential market than it would have been five or ten years ago. You infrequently can’t find 500 square feet on a residential customer’s home where you can put up panels. The second component is aesthetics are clearly important: people want to make sure they have something that looks good, but they want to make sure it’s really going to generate. Depending on where your customer is and what the application is that can be important. Lastly, I think that there is – if you think about it on the inverter side, that’s an area where we’re starting to see more innovation and more products come out whether it’s effectively charge controllers for PV systems that allow you to manage shading. We’ve seen some announcements of that here at the show. Or applications like nphase inverters which are micro-inverters that are panel-attached. Those are become more popular and fitting into the designs. Definitely popular to end customers in so much as monitoring capabilities have a stickiness factor to them especially in the retail marketplace that is very attractive. The tradeoff typically with those applications is they increase the installed cost/Watt so you have to balance that as what is my total cost based on this customer and what is the value.

The reality is there are two ‘greens’ in our business. The first green is cash: how much is this going to cost and how much am I going to save? The second green is ‘I feel good about doing this’. Any equipment that addresses t is the second green as their primary value proposition typically don’t do well vis-à-vis the ones that do a good job on the first value proposition.

Q: Some PV panels are manufactured in China using the most expensive materials possible. Even though they do offer guarantees of 20 years or 25 years, I would question the long-term reliability. Does that come up?

A: We have gone with market leaders as a company. Our panel suppliers are SunPower, Sharp and Sunteh. There are a lot of things that are available that can be at more competitive prices but to your point I don’t think it’s a balanced approach to providing value and reliability to get that power. If you pay 20% less for a panel and it generates for well over 7 years but then you find that half of your array is out, you may have chewed through all the savings in your value if you’re a retail customer. You’ve got to be careful about being penny-wise and pound foolish over the long term investment and we feel like we have very good relationships with as well as good options for our customers on all the dimensions of efficiency, aesthetics, reliability, strength of manufacturer warranty, historic performance. If you looked at any of those three suppliers, you’d be hard-pressed to say they’re not leaders. We’re also not speculating with technology that is untested or manufacturers that are untested.

Thursday, October 22, 2009

A Reality Check with Intel

The 55th International Electron Devices Meeting (IEDM) will be held next month, from December 7-9, at the Hilton Baltimore. One of the highlights of the year for us tech editors is when we receive the set of abstracts from the conference organizers, provided in advance so we can write our previews and plan our week at the conference.

The conference is well known as the place where all the major semiconductor manufacturers officially unveil the latest technology advances, where speed records are announced, and where some of the emerging, research-level types of devices are reported for the first time. This year's emerging technology session will showcase graphene nanoelectronics, including how to integrate graphene into field-effect transistors, interconnects and other IC applications; graphene-based heterojunction devices that exhibit full quantum transport; spin transport valves that may lead to spintronics-based graphene devices; and nano-electro-mechanical devices.

Spintronics-based MOSFETs will also be reported, seen as one of the alternatives once CMOS technology has outlived its usefulness. Toshiba researchers integrated ferromagnetic tunnel barriers with silicon for the first time ever and will report on it at the IEDM. The researchers will discuss fabrication techniques and observations of spin transport.

Also very much in the “cool” category is work from UC-Berkeley. At IEDM, researchers will describe a wetting-based technique used to build self-aligned organic transistors and circuits with a minimum overlap of just 0.78µm. Everything was inkjetted -- the semiconducting layers, metallization and dielectrics. The researchers say the process is simple enough that inexpensive all-printed circuits may be realized in the near future.

While it’s very easy to get excited about these and other promising advances that could potentially transform the semiconductor and related industries, a little reality check might be in order. For me, that came through an interview with Intel’s Mark Bohr, who described the company’s CPU and SoC technologies that will be presented at this year’s IEDM.

The company’s official description (provided in the tip-sheet) is this: Intel researchers will discuss a flexible, modular, mix-and-match 32-nm technology platform for advanced systems-on-a-chip (SOC) for diverse applications, including high-performance computing, low-power operation, and integrated RF/analog functions. The technology has a high-k/metal-gate architecture with three different transistor types (two with the same gate stack but different junction implants). It can support up to 11 interconnect layers, offers RF/analog passive elements, RF noise-mitigation features, and embedded memory with options for high-density (0.148µm2 cell size) or low-voltage (0.171µm). The technology demonstrated excellent reliability and enables ultra-low-power, high-performance and high-voltage-tolerant devices to be combined on the same silicon, in order to span a wide range of power, performance and feature requirements.

What’s interesting to me here is that Intel is not talking much about new process technologies, but rather the evolution of SoC. Intel first unveiled an SoC chip with the 45 nm (internally a “dot” version, the p1266.8.). With the 32 nm version and moving forward, Bohr said there are enough significant differences between the SoC and the CPU version to give its own number to the SoC version. 1268 is the CPU version, the 1269 is the SoC version of 32 nm.

Intel’s 32 nm, and most likely the 28 nm, transistors for both CPUs and SoCs use high-k metal gates (HKMG), strained silicon and employ immersion lithography. What’s interesting to me is what they do not employ: no tri-gate designs and no III-Vs in the channel region, for example. “Those types of more exotic solutions are not needed at this generation although we are continuing to explore them in our research group for future generations,” Bohr said. “Keep in mind though that high-k metal gate is still relatively new. Intel is the only company shipping high k metal gate and we did that successfully at 45 and this is the second generation so there’s still more to squeeze our of high k metal gate technology.”

Ditto for next-generation lithography solutions. “We think immersion lithography will be with us for a few more generations. We’d like to have EUV but it looks like it just won’t be ready in time for 22 nm and maybe not even for 15 nm. In the meantime, we’ll have to make do with immersion lithography and we think a greater use of double patterning techniques will be the way to do that – to extend immersion before EUV is ready. The nanoimprinting idea has been out there but I’m skeptical about whether it is going to be very viable for manufacturing applications,” Bohr said.

Instead of the exotic, Intel is instead emphasizing SoC products, which tend to require a broader range of device types. “In addition to the normal logic transistors, you need to include analog device elements such as inductors and precision capacitors. You also need to provide a wider range of transistor types from the high performance transistors used on CPUs to some very low leakage, low power transistors needed where long battery life is important. Also system on a chip products need to support a wider range of legacy I/O voltages, thus we have to add some special transistors that are tolerant to higher voltage conditions,” Bohr said.

SoC chip also have different interconnect requirements. “For the metal interconnect system for CPUs, those interconnects tend to be optimized for higher performance meaning some of the upper layers tend to use thicker and wider copper lines than the lower layers. That’s to provide higher speed interconnects across the surface of the chip. But for SoC products that run on lower frequencies, they don’t need the same higher performance interconnects. They may prefer a high density interconnect so we offer a different interconnect system for the SoC products providing fewer metal layers if low cost is important or more metal layers if increased interconnect density is important,” Bohr said. “Next we provide a range of advanced passive device elements such as precision resistors, capacitors and high-Q inductors, and a range of embedded memory from the very smallest, dense SRAM cells to low voltage SRAM to high speed SRAM. For our SoC product design, we offer this rich mix and match feature set. They can choose which features best meet the needs of their individual SoC products.”

In general, Intel plans to stay on its well established two year cadence, but moving to a dual platform approach, introducing both a CPU-specific and SoC-specific version of each technology. Production of 32 nm products is just starting this year: the end of 2011 should see 22 nm products, with 15 nm introduced at the end of 2013. How soon will we see some of the more exotic technologies such as graphene and spintronics in volume production? Not soon, given the conservative nature of the industry. Instead, it’s going to be all about integration.

Here's what Mark Bohr told me, with a few slides to illustrate his points:

"We have two papers describing our 32 nm technology that were accepted for the IEDM. The first of those two papers describes in more detail the transistors used on our high performance CPUs for 32 nm. The second paper, Intel will be disclosing for the first time the technology that we’ve developed for 32 nm SoC products. Those two technologies are very similar, they share a lot of steps, but we’ve done some extra things, added features specifically for 32 nm SoC products. Both of these technologies use our second generation high k metal gate transistors which provide the highest drive current, the lowest leakage current and the tightest transistor gate pitches of any reported 32 nm or 28 nm technology.

The third key message is our 32 nm CPU process is certified. We have Westmere CPU wafers moving through the factory in support of a plan to keep with our revenue projection.

We reached a milestone on our 45 nm technology. We’ve shipped more than 200 million CPUs on that technology using high k plus metal gate transistors. That successful experience at 45 nm will help lead to a successful ramp of 32 nm products.

Regarding Intel's naming system for the various logic technologies we’re developing or have in manufacturing: Not only are we continuing a 2 year cadence between technology generations but we’re now developing both CPU and SoC versions of each of these generations. The 45 nm generation, the CPU version is named p1266, the SoC is what we call the 1266.8. But now with the 32 nm generation, not only do we have these two versions but we’ve recognized that there are enough significant differences between the SoC and the CPU version to give its own number to the SoC version. 1268 is the CPU version, the 1269 is the SoC version of 32 nm. We’ll continue this going forward. At the 22 nm generation we’ll have both the P1270 and the 1271 for SoC products.

At 45 nm we were the first to introduce high k plus metal gate transistors, started shipping in volume in November of 2007 and so far we’re the only company shipping high k metal gate. It’s now down to very low defect levels and it is Intel’s highest yielding process ever. Even with the introduction of these revolutionary high k plus metal gate transistors, we have also achieved the highest yielding process ever.

Intel's CPUs range from a single core up to eight cores. A back of the envelope calculation: 200 million CPUs adds up to more than 50 quadrillion transistors. That’s a five with 15 zeros after it. That’s enough for every 7 million transistors for every man, woman and child on our planet!

This is the second generation of high k metal gate transistor technology. We use 9 copper plus low k interconnect layers. This generation we’re introducing immersion lithography and that provides about a 0.79% scaling of the minimum pitches. This technology is also lead-free and halogen free packages.

The following graphic illustrates Intel’s trend in scaling the transistor gate pitch which is probably the most important design rule on a logic technology. It’s an indication of how closely you can pack transistors together. We’ve been scaling that design rule by about .7X every generation and now with the 32 nm generation, it’s been scaled down to a pitch of 112.5 nm. That is the tightest gate pitch of any reported 32 nm or 28 nm technology.

Some may have the impression that a 28 nm technology might be denser to what Intel has at 32, that’s not the case at least in the case of transistor gate pitch.

Intel's trend for increasing transistor drive currents is certainly an important factor in performance. While we’ve been scaling gate pitch, we’ve also been able to continually increase drive current through the introduction of things like strained silicon technology at the 90 nm generation, then high k metal gates at 45. The driver currents on our 32 nm process are the highest reported drive currents for any reported 32 nm or 28 nm technology.

Here we illustrate Intel’s tick tock development model showing how every year we alternate between introducing a new micro architecture or introducing a new generation of process technology. Westmere is the name of the first product on our 32 nm technology. This is referred to as a tick product in the tick-tock scheme because it is the first product on our new process generation while retaining or extending the micro-architecture that was introduced on the 45 nm Nehalem product. If you recall, Intel did our first public demonstration of our Westmere CPU chips working in systems back in January of this year. Now we’re about to enter the fourth quarter and we’ve begun our production ramp for Westmere.

Defects have come down rapidly. Yields are now high. They are up to the level needed to begin a production ramp. The defect trend is offset by less than two years compared to our various successful 45 nm technology. Our process is certified and CPU wafers are now moving through the factory in support of planned Q4 revenue projections.

As we announced in February. Intel has four factories coming up on the 32 nm technology. D1D in Oregon is the first followed by D1C in Oregon, Fab32 in Arizona and Fab11X in New Mexico. Intel is investing about $7B in these factories to install the equipment and get them ready for manufacturing 32 nm products. D1D the equipment has been installed for some time now. We’ve already begun the production of the Westmere chips. D1C is just finishing the installation of that equipment. Fab32 and Fab 11X are in the process of installing equipment.

All for now.. stay tuned for my compelling Q&A!

Thursday, September 24, 2009

Getting Fired up About Solar at EUPVSEC

The EUPVSEC (European photovoltaic solar energy conference and exhibition) was well attended, with 4000 registrants from 73 countries. More than 39% were from Germany and only 11% from the U.S. 943 exhibitors represented 34 countries, 49% from Germany, 10% from China and 9% from the U.S. By my rough estimate, about 1/3 of the exhibitors were pv cell/module suppliers, predominantly crystalline silicon, the rest thin film solar. The other 2/3ds were equipment and materials suppliers, along with quite a few BOS suppliers (inverters and the like).

It was like drinking from the proverbial fire hose in some ways, but whether through luck or my natural inclination, I wound up speaking with quite a few people involved in one particular aspect of the manufacturing business: the screen printing/drying/firing of conductive pastes. This blog will provide off-the-cuff take-aways from those conversations.

To digress just slightly, I can say that crystalline silicon is alive and well. There’s no question that much of the new capacity that has been recently added or is in the works is crystalline silicon (mostly mulitcrsytalline but some poly). Much of the focus of new equipment introductions is indeed aimed at that market – not so much in terms of advancing the technology (although there was some of that in terms as such “advanced” tech as more sophisticated process control) but more on increasing throughput and reducing breakage.

Throughput is frankly staggering compared to what’s found in semiconductor manufacturing. Typically numbers are 2400 wafers per hour, with capability to extend to more than 3000 wafers per hour. Almost all tools are belt-drive in-line tools (at least in screen printing/drying/firing). Increasing throughput is typically a matter of adding more modules to the in-line system: wafers need to see a certain amount of temperature over time so a longer furnace/firing section enables the wafers to be pushed through faster yet see the same amount of temperature (or the same amount of heat to be more precise).

Throughput can also be increased by putting two or three wafers across the belt instead of just one, as least in the drying/firing stage. The challenge in doing so is that the volatile organic compounds (VOCs) produced as the paste cures are fairly nasty to handle. They are can collect on chamber surfaces and then drop onto the wafer (if not properly removed) and I suppose pose some health hazards (if I was working with these machines on a daily basis I’d be VERY concerned about how these VOCs are captured and exhausted and potential exposure levels).

Now for a word about printing conductive pastes. Silver-based pastes go on the top of the wafer in thin grid lines and thicker bus bars. Aluminum-based pastes go on the back of the wafer in a blanket film (the whole thing forming a simple p-n junction).

Because it’s desirable to block as little light as possible from entering the cell, the top lines should be very thin. Yet, they need to carrying an acceptable amount of current for optimal efficiency. Because screen printers can only deposit films with a thickness of about 20-25 microns, a double print process has come into play, where the bottom line is printed and dried. The wafers are flipped and the backside contact is applied and dried. Again the wafers are flipped and a second front side line is applied directly on top of the first. It’s desirable for this line to be “high and tight” with straight vertical profiles to maximize conductivity.

An added complexity to this whole scenario is that there’s a push to make wafers thinner in order to minimize costs/achieve optimal out put of the wafering process (wafers are typically sawn with a wire saw from a brick into wafers – making them thinner means more wafers/brick). Wafers are now typically 190-200 microns thick. There’s a push to make then 140 microns or thinner. This, of course, increase the chance of the inevitable breakage. “Acceptable” breakage numbers I heard at the show range from 1 in 3000 to 1 in 5000 to 1 in 10000. The suppliers I talked to seemed confident about the ability to keep breakage under control, it being mostly a matter of how the wafers are handed off to and from a fast and slow belt respectively (machines may have three different belts moving at different speeds to optimize drying/firing conditions).

Work is underway to develop new conductive pastes that provides a better profile control when printed in thick layers. Sources say 5-6 suppliers are pursuing new technologies, some including nanocomposites to achieve the desired results. It’s not all that different from the conductive pastes used in surface mount technology, so perhaps my colleagues at SMT might have some insight here.

One final note: the heating technology used in drying and firing furnaces is typically either convection heating, infrared lamps or uv lamps. Surprisingly, there was little discussion about many of the things that are well known issues in the semiconductor such as the size of the grain, grain boundary interfaces, the structure of the grain, etc., all of which can have a significant impact on resistivity.

One postscript: IMEC was promoting the idea of electrochemical deposition of copper lines as an alternative to silver. Copper lines are cheaper and can easily be printed at finer dimensions. Also new: Applied Materials introduced the concept that it was possible to achieve higher efficiencies, but by going from 9 process steps to 14. No doubt this is true, but guess who would supply the five new steps?!?

More later… all I can say is I am fired up about PV (in my best Governator accent).

Thursday, September 3, 2009

Welcome to ElectroIQ!

Here you will find easy access to five different PennWell brands that address Electronics and Electronics Manufacturing: Solid State Technology, Photovoltaics World, Small Times, Advanced Packaging and SMT. Each brand corresponds to one of our topic centers: semiconductors, photovoltaics, nanotech MEMS, and surface mount technology. Navigate through our topic and subtopic centers to find the latest news and tech features, or use the search function to access all of our content, including the archives. It’s all here!

The reasoning behind ElectroIQ is simple. Increasingly, similar process technologies are being applied across the various industries addressed by our five different brands. Screen printing of conductive pastes, for example, is used in printed circuit board assembly as well as photovoltaics manufacturing. 3D integration is an Advanced Packaging concept, but largely uses semiconductor front end process type steps. Chips are being embedded in printed circuit boards, nanotechnology is being implemented in semiconductor manufacturing and packaging materials. MEMS are integrated (and packaged) with energy harvesting devices and thin film batteries. The list goes on, up and down -- and across-- the entire supply chain.

We’ve worked hard to make sure that each brand continues to maintain its own identity, and that you know the source of everything you read. What we’re excited about is that with the increased functionality of the new site (made possible by a new software platform), we'll be able to more easily identify and link to content that applies to our many different topic centers.

Coinciding with the new launch, we have restructured our editorial team. Debra Vogler, based in San Jose, will handle all technical feature content and submissions for SST, Advanced Packaging, Photovoltaics World and Small Times ( Jim Montgomery ( is responsible for news posting and wire news feed. Please direct press releases and news leads to him. New to the team is Steve Smith ( who has taken on Managing Editor responsibilities.

Heading up SMT editorial efforts is Meredith Courtemanche ( All editorial submissions and inquiries regarding SMT should be directed to her.

Welcome again. As always, please let me know what you think! You can reach me by e-mail at or by phone at 603-891-9217.

Pete Singer
Editorial Director

Tuesday, August 18, 2009

The Lean Manager: A Novel

I just started reading a new book titled "The Lean Manager, A Novel of Lean Transformation," and I'm already hooked. The authors, Michael and Freddy Balle, have taken what some would consider a pretty dry topic -- the Toyota Production System -- and brought it to life through a character by the name of Jenkinson, a new CEO at a fictional manufacturing plant.

A quick excerpt:

"Jenkinson stopped in front of a press, watching the robot hand slide in and out of the mold, picking up the finished part and dropping it on the conveyor, where an operator would deburr the part and place it in the customer packaging.

"Weekend shifts?"

"At the moment, we've had some press breakdowns so we need to catch up, and we've still got the parts that were supposed to be transferred to Romania. We're running seven days a week on those."

"Come on!" the CEO had exclaimed irritably, with an outstretched hand encompassing the press area. "Look around you, a third of your presses are standing idle!"

Ward kept his expression carefully blank, and said nothing. What was there to say?"

I never thought I'd read a novel that casually incorporates EPITDA and injection molding, but so far, so good. Now, how to apply it to the publishing business?